Integrated gate driver

ABSTRACT

A gate driver suitable for integration with the backplane of an AMOLED display includes first and second clock signal sources producing first and second clock signals each having alternating active and inactive portions configured such that when one of the clock signals is active the other of the clock signals is inactive, and active portions of the first and second clock signals do not overlap. In a daisy chain of circuits for producing gate signals, each of the circuits except the last has an output coupled to the input of the next circuit in the chain. A source of a start token signal is coupled to an input of a first circuit in the daisy chain. Each of the circuits is configured to produce a gate signal one clock cycle after an active portion of one of the clock signals is received.

CROSS REFERENCE TO RELATED APPLICATION

This application claims the benefit of U.S. Provisional Application No.61/969,533, filed Mar. 24, 2014, and U.S. Provisional Application No.61/975,321, filed Apr. 4, 2014, each of which is hereby incorporated byreference herein in its entirety.

FIELD OF THE INVENTION

The present disclosure relates generally to AMOLED displays. Morespecifically, this disclosure relates to gate drivers suitable forintegration into the back plane of an AMOLED display, which typicallyuses thin film transistors (TFTs).

BACKGROUND

Traditionally, when building AMOLED displays, it has been the practiceto manufacture the display panel backplane and the gate drivers asseparate devices. Doing so allows different manufacturing techniques tobe applied to each case. If the same techniques could be used tomanufacture the gate driver and the display itself, i.e., if the gatedriver could be integrated into the back plane of the display, then theycould be manufactured simultaneously with fewer components and lessassembly required, leading to lower cost displays.

SUMMARY

In accordance with one embodiment, a gate driver suitable forintegration with the backplane of an active matrix organic lightemitting diode (AMOLED) display comprises clock signal sources producingfirst and second clock signals each having alternating active andinactive portions configured such that when one of the clock signals isactive the other of the clock signals is inactive, and active portionsof the first and second clock signals do not overlap; a daisy chain ofcircuits for producing gate signals, each of the circuits except thelast circuit in the chain having an output coupled to the input of anadjacent circuit in the daisy chain; and a source of a start tokensignal coupled to an input of a first circuit in the daisy chain;wherein each of the circuits is configured to produce a gate signal oneclock cycle after an active portion of one of the clock signals isreceived.

In one implementation, the gate driver is configured for use with anAMOLED display comprising p-type transistors so that an active signalcorresponds to a low voltage and an inactive signal corresponds to ahigh voltage. The gate signals are active low for selecting oraddressing p-type thin film transistors, or active high for selecting oraddressing n-type thin film transistors.

Adjacent circuits in the daisy chain produce consecutive gate signalswith a predetermined time interval between each pair of consecutive gatesignals. The active portions of the first and second clock signalspreferably have a predetermined time interval between them, to producethe predetermined time interval between each pair of consecutive gatesignals.

In accordance with another embodiment, an integrated gate driver forperforming emission operations comprises a source of first and secondclock signals each, having alternating active and inactive portionsconfigured such that when one is active the other is inactive and activesignals do not overlap; a start token signal source and an inverse starttoken signal source for input into a first circuit block. Alternatingodd and even circuit blocks are daisy chained together such that theoutput of one circuit block is connected to the input of the nextcircuit block, and each circuit block receives as inputs both first andsecond clock signals, wherein each circuit block is configured toproduce an active output one clock cycle after an active signal isreceived and an inactive output at all other times. This gate driver maybe configured for use with a display comprising p-type transistors sothat an active signal corresponds with a high voltage and an inactivesignal corresponds with a low voltage. The alternating circuit blocksare configured to select a line of pixels for two clock cycles in orderto allow time for the pixels to settle before being programmed.

The foregoing and additional aspects and embodiments of the presentdisclosure will be apparent to those of ordinary skill in the art inview of the detailed description of various embodiments and/or aspects,which is made with reference to the drawings, a brief description ofwhich is provided next.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other advantages of the disclosure will becomeapparent upon reading the following detailed description and uponreference to the drawings.

FIG. 1A is a block diagram of a display system using an integrated gatedriver.

FIG. 1B is a block diagram of a select signal driver for the array ofpixel circuits in the display of FIG. 1A.

FIG. 2A is a circuit diagram of a circuit for use in an odd block ofFIG. 1B when configured as an active low select signal driver.

FIG. 2B is a circuit diagram of a circuit for use in an even block ofFIG. 1B when configured as an active low select signal driver.

FIG. 2C is a timing diagram illustrating the operation of the circuitsof FIGS. 2A and 2B.

FIG. 3A is a circuit diagram of a circuit for use in an odd block ofFIG. 1B when configured as an active high select signal driver.

FIG. 3B is a circuit diagram of a circuit for use in an even block ofFIG. 1B when configured as an active high select signal driver.

FIG. 3C is a timing diagram illustrating the operation of circuits ofFIGS. 3A and 3B.

FIG. 4A is a circuit diagram of a second circuit for use in an odd blockof FIG. 1B when configured as an active high select signal driver.

FIG. 4B is a circuit diagram of a second circuit for use in an evenblock of FIG. 1B when configured as an active high select signal driver.

FIG. 5A is a circuit diagram of a third circuit for use in an odd blockof FIG. 1B when configured as an active high select signal driver.

FIG. 5B is a circuit diagram of a third circuit for use in an even blockof FIG. 1B when configured as an active high select signal driver.

While the present disclosure is susceptible to various modifications andalternative forms, specific embodiments or implementations have beenshown by way of example in the drawings and will be described in detailherein. It should be understood, however, that the disclosure is notintended to be limited to the particular forms disclosed. Rather, thedisclosure is to cover all modifications, equivalents, and alternativesfalling within the spirit and scope of an invention as defined by theappended claims.

DETAILED DESCRIPTION

FIG. 1A shows a display 10 for use with an integrated gate driver 12.Display 10 comprises an array (m×n) of pixels. FIG. 1B shows a blockdiagram of an integrated select signal driver 100 for the array of pixelcircuits in the display of FIG. 1A. It should be noted that althoughselect driver 100 is shown, and discussed below, as driving rows (1 ton), it may also be implemented to drive columns (1 to m). Select driver100 comprises a series of alternating odd blocks 101 and even blocks 102daisy chained together so that the output of each block, e.g., SEL(1),both drives its associated row of pixels and serves as an input to thefollowing block. Accordingly, rows can be selected and driven insequence. Other inputs clk1 and clk2 from clock signal sources are usedto regulate timing and are discussed in greater detail below. A starttoken signal ST from a start token signal source is used to initiate therow driving sequence.

Exemplary embodiments of select driver 100 are discussed below. In eachcase, it is assumed that all transistors are p-type transistors, and aretherefore active low devices. Those of skill in the art will understandthat complementary circuit designs can be used with active high orn-type transistors. Alternatively, a combination of p-type and n-typedevices may be used to implement select signal driver 100.

FIGS. 2A and 2B show circuit diagrams for use in odd blocks 201 and evenblocks 202 corresponding to blocks 101 and 102 of FIG. 1B whenconfigured as an active low select signal driver suitable for use as aselect driver during read or write operations.

Physically, the circuit elements in odd blocks 201 and even blocks 202are identical. The difference between odd blocks 201 and even blocks 202is the inputs. The signals clk1 and clk2 play complementary roles in oddand even circuit blocks. It should be noted that in this implementationonly one of clk1 and clk2 may be active at any given time; active clocksignals do not overlap, but inactive clock signals may overlap duringperiods where the signals are transitioning. Other combinations of clk1and clk2 may be used to achieve similar or extra functionality.

In operation a sequence proceeds through several time periods, a subsetof which is shown as 280 to 292 in FIG. 2C. It should be noted that sometime periods are longer than others and that the sequence proceeds byalternating long and short periods. For example, a longer period 280-281is followed by a short period 281-282 which is followed by a longerperiod 282-283. In actual operation, the number of time periods will berelated to the number of rows in the display. V_(gh) is a voltage thatcorresponds to a high, therefore inactive, signal while V_(gl)corresponds to a low, therefore active, signal. V_(gh) and V_(gl) areeither fixed or adjustable voltages provided by the power supply unit(not shown) of the display system 10.

Referring to FIGS. 2A and 2C, the operation of an odd block proceeds asfollows. Block 1 will be described as an example.

At 280, Start Token (ST) and clk2 go low, therefore active, while clk1goes high, therefore inactive. This causes transistor switches Tc, Teand Tg to close. The low ST signal will expose the bottom plate ofcapacitor Ca to a low signal, bring a low signal to point A 205 andcause transistor switches Ta and Tf to close. This allows a high signalto reach point B 207 which exposes the bottom plate of Cb to a highsignal and causes transistor switches Tb and Td to open. Accordingly,SEL(1) goes out high as it is being fed from V_(gh) via Tc and high clk1via Ta.

At 281, clk2 goes high, causing Tc, Te and Tg to open.

At 282, clk1 goes low while ST goes high. ST will stay high for theremainder of the sequence. Capacitor Ca will maintain a low signal atpoint A 205 and keep Ta and Tf closed. Capacitor Cb will maintain a highsignal at point B 207 and keep Tb and Td open. Accordingly, SEL(1)output will be low as it is being fed from low clk1 via Ta.

At 283, clk1 goes high causing SEL(1) to go high.

At 284, clk2 goes low causing Tc, Te and Tg to close. The high ST signalwill expose the bottom plate of capacitor Ca to a high signal, bring ahigh signal to point A 205 and cause transistor switches Ta and Tf toopen. This brings a low signal, V_(gl), to point B 207 which exposes Cbto a low signal and causes Tb and Td to close. Accordingly, SEL(1) goesout high as it is being fed from V_(gh) via Tb and Tc.

At 285, clk2 goes high causing Tc, Te and Tg to open.

At 286, clk1 goes low. Capacitor Ca will maintain a high signal at pointA 205 and keep Ta and Tf open. Capacitor Cb will maintain a low signalat point B 207 and keep Tb and Td close. Accordingly, SEL(1) will remainhigh since it is being fed from V_(gh) via Tb.

At 287, clk1 goes high.

Since ST will not change again until the entire sequence needs to berepeated, block 1 will simply repeat the pattern of 284 to 287 until theST is changed, regardless of the state of clk1 and clk2. For example,the circuit will proceed through the same states from 288-291 as it didfrom 284-287 and SEL(1) will remain high.

Referring to FIGS. 2B and 2C, the operation of an even block proceeds asfollows. Block 2 will be described as an example. It should be notedthat the operation of an even block is complementary to the operation ofan odd block in that clk1 and clk2 play opposite roles.

At 282, SEL(1) and clk1 go low, therefore active, while clk2 is high,therefore inactive. This causes transistor switches Tc, Te and Tg toclose. The low SEL(1) signal will expose the bottom plate of capacitorCa to a low signal, bring a low signal to point A 206 and causetransistor switches Ta and Tf to close. This allows a high signal toreach point B 208 which exposes the bottom plate of Cb to a high signaland causes Tb and Td to open. Accordingly, SEL(2) goes out high as it isbeing fed from V_(gh) via Tc and high clk2 via Ta.

At 283, clk1 goes high, causing Tc, Te and Tg to open. SEL(1) will alsogo high and stay high for the remainder of the sequence. Capacitor Cawill maintain a low signal at point A 206 and keep Ta and Tf closed.Capacitor Cb will maintain a high signal at point B 208 and keep Tb andTd open.

At 284, SEL(2) and clk2 go low while SEL(1) remains high. Thus, there isa time interval (284-283) between clk1 going high and clk2 going low,and also between SEL(1) going high and SEL(2) going low.

At 285, clk2 goes high causing SEL(2) to go high.

At 286, clk1 goes low causing Tc, Te and Tg to close. The high SEL(1)signal will now expose the bottom plate of capacitor Ca to a highsignal, bring a high signal to point A 206 and cause transistor switchesTa and Tf to open. This brings a low signal, V_(gl), to point B 208which exposes the bottom plate of Cb to a low signal and causes Tb andTd to close. Accordingly, SEL(2) goes out high as it is being fed fromV_(gh) via Tb and Tc.

At 287, clk1 goes high causing Tc, Te and Tg to open. Capacitor Ca willmaintain a high signal at point A 206 and keep Ta and Tf open. CapacitorCb will maintain a low signal at point B 208 and keep Tb and Td closed.

At 288, clk2 goes low. Accordingly, SEL(2) will remain high since it isbeing fed from V_(gh) via Tb.

At 289, clk2 goes high.

Since SEL(1) will not change again until the entire sequence needs to berepeated, block 2 will simply repeat the pattern of 286 to 289,regardless of the state of clk1 and clk2, until SEL(1) changes. Forexample, the circuit will proceed through the same states from 290-293as it did from 286-289 and SEL(2) will remain high.

All the odd blocks with follow the same pattern described for block 1and all even block will follow the same pattern described for block 2,only delayed since the input of each block is the output of the previousblock. In this way, each row of the display 10 may be selected anddriven exclusively.

A pixel circuit in an (m×n) array, such as display system 10, mayrequire multiple select signals to operate. An example of typical SELsignals used in a display system is write (WR), read (RD) and emission(EM). The circuits described above in FIGS. 2A-2C are suitable for WRand RD functions, but not for EM functions. Since emission is active lowin a display comprising p-type transistors, a signal to tell a row tostop emitting will be active high.

FIGS. 3A and 3B show circuit diagrams for use in odd blocks 301 and evenblocks 302 corresponding to 101 and 102 in FIG. 1B when configured as anactive high select signal driver. Note that the circuits of FIGS. 3A and3B are designed to hold EM signals high for twice as long in order toallow time for the components in the pixels to settle beforeprogramming.

Physically, the circuit elements in odd blocks 301 and even blocks 302are identical. The difference between odd blocks 301 and even blocks 302is the inputs. Clk1 and clk2 play complementary roles in odd/evenblocks. It should be noted that only one of clk1 and clk2 may be activeat any given time in this implementation; active clock signals do notoverlap. Other combinations of clk1 and clk2 may be used to achievesimilar or extra functionality.

In operation a sequence proceeds through several time periods, a subsetof which are shown as 380 to 392 in FIG. 3C. It should be noted thatsome time periods are longer than others and that the sequence proceedsby alternating long and short periods. For example, a longer period380-381 is followed by a short period 381-382 which is followed by alonger period 382-383. In actual operation, the number of time periodswill be related to the number of rows in the display system 10. V_(gh)is a voltage that corresponds to a high, therefore inactive state,signal while V_(gl) corresponds to a low, therefore active state,signal.

Referring to FIGS. 3A and 3C, the operation of an odd block proceeds asfollows. Block 1 will be described as an example. Note that anunderscore, “_” indicates a signal in an inverse state. For example, STand ST_ will always have inverse states; ST_ will be low when ST is highand vice versa.

At 380, ST_ and clk2 go low, while ST and clk1 go high. This causestransistor switches T3, T6, T7 and T10 to close. The high ST signal willexpose the bottom plate of capacitor C4 to a high signal, cause T4 toopen and bring a high signal to point A 303 which exposes the bottomplate of C1 to a high signal and causes T11, T5 and T2 to open. The lowST_ signal will expose the bottom plate of capacitor C3 to a low signaland cause transistor switch T8 to close and bring a low signal to pointB 305 which exposes the bottom plate of C2 to a low signal and causesT12, T9 and T1 to close. Accordingly, EM(1) will be high and EM_(1) willbe low.

At 381, clk2 goes high, causing transistors T3, T6, T7 and T10 to close,effectively shutting out ST and ST_ signals. Capacitor C4 will maintaina high signal and keep T4 open while C3 will maintain a low signal andkeeps T8 closed. Capacitor C2 will maintain a low signal at point B 305and keep transistors T12, T1 and T9 closed while C1 maintains a highsignal at point A 303 and keeps T11, T2 and T5 open. Accordingly, EM(1)will remain high while EM_(1) will remain low.

At 382, clk1 goes low but has no effect on the output of block 1, EM(1)and EM_(1). Before 383, ST goes low and ST_ goes high, but has no effectsince the transistors controlled by clk2 are closed.

At 383, clk1 goes high.

At 384, clk2 goes low causing transistor switches T3, T6, T7 and T10 toclose. The low ST signal will expose the bottom plate of capacitor C4 toa low signal, cause T4 to close and bring a low signal to point A 303which exposes the bottom plate of C1 to a low signal and causes T2, T5and T11 to close. The high ST_ signal will expose the bottom plate ofcapacitor C3 to a high signal, cause T8 to open and bring a high signalto point B 305 which exposes the bottom plate of C2 to a high signal andcauses T1, T9 and T12 to open. Consequently, EM(1) will turn low whileEM_(1) turns high.

At 385, clk2 goes high, causing T3, T6, T7 and T10 to close. CapacitorC4 will maintain a low signal and keep T4 closed while C3 maintains ahigh signal and keeps T8 open. Capacitor C2 will maintain a high signalat point B 305 and keep transistor switches T1, T9 and T12 open while C1maintains a low signal at point A 303 and keeps T2, T5 and T11 closed.Accordingly, EM(1) will remain low while EM_(1) remains high.

At 386, clk1 goes low.

At 387, clk1 goes high but has not effect on the output of block 1,EM(1) and EM_(1).

Since ST and ST_ inputs will not change again until the entire sequenceneeds to be repeated, block 1 will simply repeat the pattern of 384 to387, regardless of the state of clk1 and clk2, until the inputs arechanged. For example, the circuit will proceed through the same statesfrom 388-391 as it did from 384-387. EM(1) will remain low and EM_(1)will remain high.

Referring to FIGS. 3B and 3C, the operation of an even block proceeds asfollows. Block 2 will be described as an example.

At 382, EM_(1) and clk2 go low while EM(1) and clk1 go high. This causesT3, T6, T7 and T10 to close. The high EM(1) signal will expose thebottom plate of capacitor C4 to a high signal, cause T4 to open andbring a high signal to point A 304 which exposes the bottom plate of C1to a high signal and causes T11, T5 and T2 to open. The low EM_(1)signal will expose the bottom plate of capacitor C3 to a low signal andcause transistor T8 to close and bring a low signal to point B 306 whichexposes the bottom plate of C2 to a low signal and causes T12, T9 and T1to close. Accordingly, EM(2) will go high and EM_(2) will turn low.

At 383, clk1 goes high, causing transistors T3, T6, T7 and T10 to open,effectively isolating the EM(1) and EM_(1) signals into block 2.Capacitor C4 will maintain a high signal and keep T4 open while C3 willmaintain a low signal and keep T8 closed. Capacitor C2 will maintain alow signal at point B 306 and keep transistor switches T12, T1 and T9closed while C1 maintains a high signal at point A 304 and keeps T11, T2and T5 open. Accordingly, EM(2) will remain high while EM_(2) willremain low.

At 384, clk2 goes low but has not effect on the output, EM(2) andEM(_(2), of block 2.

At 385, clk2 goes high, which also has no effect on the output of block2.

At 386 clk1 goes low causing transistor switches T3, T6, T7 and T10 toclose. The low EM(1) signal will expose the bottom plate of capacitor C4to a low signal, cause T4 to close and bring a low signal to point A 304which exposes the bottom plate of C1 to a low signal and causes T2, T5and T11 to close. The high EM_(1) signal will expose the bottom plate ofcapacitor C3 to a high signal, cause T8 to open and bring a high signalto point B 306 which exposes the bottom plate of C2 to a high signal andcauses T1, T9 and T12 to open. Accordingly, EM(2) will turn low whileEM_(2) turns high.

At 387, clk1 goes high, causing T3, T6, T7 and T10 to close. CapacitorC4 will maintain a low signal and keep T4 closed while C3 maintains ahigh signal and keeps T8 open. Capacitor C2 will maintain a high signalat point B 306 and keep transistors T1, T9 and T12 open while C1maintains a low signal at point A 304 and keeps T2, T5 and T11 closed.Accordingly, EM(2) will remain low while EM_(2) remains high.

At 388, clk2 goes low and has no effect on the output of block 2.

At 389, clk1 goes high and also has no effect on the output of block 2.

Since EM(1) and EM_(1) inputs will not change again until the entiresequence needs to be repeated, block 2 will simply repeat the pattern of386 to 389, regardless of the state of clk1 and clk2, until the inputsare changed. For example, the circuit will proceed through the samestates from 390-393 as it did from 386-389. EM(2) will remain low andEM_(2) will remain high.

An analogous pattern will occur in subsequent odd blocks. Acomplementary analogous pattern, with clk1 and clk2 playing oppositeroles, will occur in subsequent even blocks.

FIGS. 4A and 4B show circuit diagrams of a second embodiment of oddblocks 401 and even blocks 402 of FIG. 1B when configured as an activehigh select signal driver. The circuits of FIGS. 4A and 4B are identicalto those of FIGS. 3A and 3B except for one connection of capacitor C2.In FIGS. 4A and 4B the terminals of C2 are connected to point B and theEM_(—) output rather than point B and clk1 or clk2. Clk1 and clk2 nowdrive EM_(1) through T12. The timing diagram of FIG. 3C also applies tothe circuits in FIGS. 4 and 4B.

It has been found that the circuits of FIGS. 4A and 4B are better ableto handle variations in T12 than those shown in FIGS. 3A and 3B.

FIGS. 5A and 5B show circuit diagrams of a third embodiment of oddblocks 501 and even blocks 502, corresponding to 101 and 102 of FIG. 1B,when configured as an active high select signal driver. The circuits ofFIGS. 5A and 5B are identical to those of FIGS. 3A and 3B except that C1has been removed and T10 has been replaced by a resistance, R, connectedto voltage V₁, where V₁<V_(gl). The circuits shown in FIGS. 5A and 5Bprovide a more stable voltage at point A.

Physically, the circuit elements in odd blocks 501 and even blocks 502are identical. The difference between odd blocks 501 and even blocks 502is the inputs. Clk1 and clk2 play complementary roles in odd/evenblocks. It should be noted that only one of clk1 and clk2 may be activeat any given time in this implementation; active clock signals do notoverlap. Other combination of clk1 and clk2 may be used to achievesimilar or extra functionality.

In operation, a sequence proceeds through several time periods, a subsetof which are shown as 380 to 392 in FIG. 3C. It should be noted thatsome time periods are longer than others and that the sequence proceedsby alternating long and short periods. For example, a longer period,380-381, is followed by a short period, 381-382 which is followed by alonger period, 382-383. In actual operation, the number of time periodswill be related to the number of rows in display system 10. V_(gh) is avoltage that corresponds to a high, therefore inactive state, signalwhile V_(gl) corresponds to a low, therefore active state, signal andV₁<V_(gl).

Referring to FIGS. 5A and 3C, the operation of an odd block proceeds asfollows. Block 1 will be described as an example. Note that a “_”indicates an inverse state. For example, ST and ST_(—) will always haveinverse states; ST_(—) will be low when ST is high and vice versa.

At 380, ST_ goes low, while ST and clk1 go high. Clk2 is also low atthis time. This causes transistors T3, T6 and T7 to close. The high STsignal will expose the bottom plate of capacitor C4 to a high signal andcause T4 to open. The low ST_ signal will expose the bottom plate ofcapacitor C3 to a low signal and cause T8 to close and bring a lowsignal to point B 505 which exposes the bottom plate of C2 to a lowsignal and causes T12, T9 and T1 to close. Since T8 and T9 are closed,and by design the on-resistance of T8 and T9 is much less than R, a highsignal reaches point A, exposes the bottom plate of C1 to a high signaland causes T11, T5 and T2 to open. Accordingly, EM(1) will be high andEM_(1) will be low.

At 381, clk2 goes high, causing transistors T3, T6 and T7 to open,effectively shutting out ST and ST_ signals. Capacitor C4 will maintaina high signal and keep T4 open while C3 will maintain a low signal andkeep T8 closed. Capacitor C2 will maintain a low signal at point B 505and keep T12, T1 and T9 closed. Since T8 and T9 are closed, and bydesign the on-resistance of T8 and T9 is much less than R, a high signalreaches point A 503, exposes the bottom plate of C1 to a high signal andcauses T11, T5 and T2 to open. Accordingly, EM(1) will remain high whileEM_(1) will remain low.

At 382, clk1 goes low. Before 383, ST goes low and ST goes high, but hasno effect since the transistors controlled by clk2 are open.

At 383, clk1 goes high.

At 384 clk2 goes low causing T3, T6 and T7 to close. The low ST signalwill expose the bottom plate of capacitor C4 to a low signal and causeT4 to close. The high ST_ signal will expose the bottom plate ofcapacitor C3 to a high signal, cause T8 to open and bring a high signalto point B 505 which exposes the bottom plate of C2 to a high signal andcauses T1, T9 and T12 to open. Since T8 and T9 are open, V₁ is the onlysignal source able to reach point A 503. This brings a low signal topoint A 503 which causes T2, T5 and T11 to close. Accordingly, EM(1)will turn low while EM_(1) turns high.

At 385, clk2 goes high, causing T3, T6 and T7 to open. Capacitor C4 willmaintain a low signal and keep T4 closed while C3 maintains a highsignal and keeps T8 open. Capacitor C2 will maintain a high signal atpoint B 505 and keep T1, T9 and T12 open. Since T8 and T9 are open, V₁is the only signal source able to reach point A 503. This brings a lowsignal to point A 503 which causes T2, T5 and T11 to close. Accordingly,EM(1) will remain low while EM_(1) remains high.

At 386, clk1 goes low.

At 387, clk1 goes high and has no effect on the outputs of block 1.

Since ST and ST_ inputs will not change again until the entire sequenceneeds to be repeated, block 1 will simply repeat the pattern of 384 to387, regardless of the state of clk1 and clk2, until the inputs arechanged. For example, the circuit will proceed through the same statesfrom 388-391 as it did from 384-387. EM(1) will remain low and EM_(1)will remain high.

Referring to FIGS. 5B and 3C, the operation of an even block proceeds asfollows. Block 2 will be described as an example.

At 382, clk1 goes low, while EM(1) and clk2 are high. EM_(1) is also lowat this time. This causes T3, T6 and T7 to close. The high EM(1) signalwill expose the bottom plate of capacitor C4 to a high signal and causeT4 to open. The low EM_(1) signal will expose the bottom plate ofcapacitor C3 to a low signal, cause T8 to close and bring a low signalto point B 506 which exposes the bottom plate of C2 to a low signal andcauses T12, T9 and T1 to close. Since T8 and T9 are closed, and bydesign the on-resistance of T8 and T9 is much less than R, a high signalreaches point A 504, exposes the bottom plate of C1 to a high signal andcauses T11, T5 and T2 to open. Accordingly, EM(2) will go high andEM_(2) will turn low.

At 383, clk1 goes high, causing transistors T3, T6 and T7 to open,effectively isolating the EM(1) and EM_(1) signals. Capacitor C4 willmaintain a high signal and keep T4 open while C3 will maintain a lowsignal and keep T8 closed. Capacitor C2 will maintain a low signal atpoint B 506 and keep transistors T12, T1 and T9 closed. Since T8 and T9are closed, and by design the on-resistance of T8 and T9 is much lessthan R, a high signal reaches point A 504, exposes the bottom plate ofC1 to a high signal and causes T11, T5 and T2 to open. Accordingly,EM(2) will remain high while EM_(2) remains low.

At 384, clk2 goes low and has no effect on the output of block 2.

At 385, clk2 goes high which also has no effect on the output of block2.

At 386 clk1 goes low causing T3, T6 and T7 to close. The low EM(1)signal will expose the bottom plate of capacitor C4 to a low signal andcause T4 to close. The high EM_(1) signal will expose capacitor thebottom plate of C3 to a high signal, cause T8 to open and bring a highsignal to point B 506 which exposes the bottom plate of C2 to a highsignal and causes T1, T9 and T12 to open. Since T8 and T9 are open, V₁is the only signal source able to reach point A 504. This brings a lowsignal to point A 504 which causes T2, T5 and T11 to close. Accordingly,EM(2) will turn low while EM_(2) turns high.

At 387, clk1 goes high, causing T3, T6 and T7 to open. Capacitor C4 willmaintain a low signal and keep T4 closed while C3 maintains a highsignal and keeps T8 open. Capacitor C2 will maintain a high signal atpoint B 506 and keep T1, T9 and T12 open. Since T8 and T9 are open, V₁is the only signal source able to reach point A 504. This brings a lowsignal to point A 504 which causes T2, T5 and T11 to close. Accordingly,EM(2) will remain low while EM_(2) remains high.

At 388, clk2 goes low and has no effect on the output of block 2.

At 389, clk1 goes high and also has no effect on the output of block 2.

Since EM(1) and EM_(1) inputs will not change again until the entiresequence needs to be repeated, block 2 will simply repeat the pattern of386 to 389, regardless of the state of clk1 and clk2, until the inputsare changed. For example, the circuit will proceed through the samestates from 390-393 as it did from 386-389. EM(2) will remain low andEM_(2) will remain high.

An analogous pattern will occur in subsequent odd blocks. Acomplementary analogous pattern, with clk1 and clk2 playing oppositeroles, will occur in subsequent even blocks.

Other permutations of the circuits shown in FIGS. 5A and 5B include:making resistance R an active element and replacing T5 and T9 withdirected connections between their adjacent transistors.

In a display system 10 implementing the integrated gate driver describedin FIG. 3, 4 or 5 under normal operating conditions, each row of pixelswill be in turn, off and being allowed to settle, off and beingprogrammed and on and emitting. Accordingly, at any given time, one rowwill be off and settling, one row will be off and being programmed andthe remainder will be emitting according to their last programmed state.

Additional functionality can be achieved by varying the inputs. Forexample, a power-on function, a light-on function and a gate outputenable (GOE) function are all possible with any of the circuitsdescribed above.

A power-on function can be used whenever display system 10 is firstpowered up or at any other time that a simultaneous reset of all SELoutputs is desired. In the circuits of FIGS. 2A and 2B, if clk1, clk2and V_(gl) are set low while V_(gh) and ST are set high then theinactive signal will propagate to the entire SEL(1) to SEL(n) of displaysystem 10 and all SEL signals will be deactivated. In the circuits ofFIGS. 3A, 3B, 4A, 4B, 5A, and 5B, if clk1, clk2, V_(gl) and ST_(—) areset low while V_(gh) and ST are set high the same result will beachieved. V₁ can be allowed to float during this operation.

A light-on function can be used to test the functionality of all thepixels by selecting and driving all rows simultaneously. In the circuitsof FIGS. 2A and 2B this can be achieved by setting all of the inputs,clk1, clk2, V_(gl), V_(gh) and ST to low. Light-on can be achieved inthe circuits of FIGS. 3A, 3B, 4A, 4B, 5A and 5B by setting inputs clk1,clk2, V_(gl), V_(gh), ST and ST_ to low. V₁ can be allowed to float.

A GOE (gate output enable) function allows an active SEL line to bemomentarily deactivated even when a token is present. This can beachieved by altering the clk1 signal input for odd blocks or the clk2signal input for even blocks. For example, consider the circuit of FIG.2A, an odd block, as it reaches time 284. Normally, clk2 would rise at284 causing the token to shift into the next block. However, if clk2 isinstead held high, a GOE function can be realized. In this situation, ifclk1 goes low again, SEL(1) will be reactivated. This can be used toimplement in-pixel compensation or to read out pixel characteristics forexternal compensation.

While particular implementations and applications of the presentdisclosure have been illustrated and described, it is to be understoodthat the present disclosure is not limited to the precise constructionand compositions disclosed herein and that various modifications,changes, and variations can be apparent from the foregoing descriptionswithout departing from the spirit and scope of an invention as definedin the appended claims.

1-15. (canceled)
 16. A gate driver suitable for integration with thebackplane of an active matrix organic light emitting diode (AMOLED)display, said gate driver comprising clock signal sources producingfirst and second clock signals each having alternating active andinactive portions configured such that when one of said clock signals isactive the other of said clock signals is inactive, and active portionsof said first and second clock signals do not overlap; a daisy chain ofcircuits integrated within said backplane for producing gate signals,each of said circuits including a capacitor and a thin film transistor,and each of said circuits except the last circuit in the daisy chainhaving an output coupled to an input of an adjacent circuit in the daisychain; and a source of a start token signal coupled to an input of afirst circuit in said daisy chain; wherein each of said circuits isconfigured to produce a gate signal one clock cycle after an activeportion of one of said clock signals is received.
 17. The gate driver ofclaim 16 which is configured for use with an AMOLED display comprisingp-type transistors so that an active signal corresponds to a low voltageand an inactive signal corresponds to a high voltage.
 18. The gatedriver of claim 16 in which said gate signals are active low forselecting or addressing p-type thin film transistors.
 19. The gatedriver of claim 16 in which said gate signals are active high forselecting or addressing n-type thin film transistors.
 20. The gatedriver of claim 16 in which said circuits produce consecutive gatesignals with a predetermined time gap between each pair of consecutivegate signals.
 21. The gate driver of claim 20 in which said activeportions of said first and second clock signals have a predeterminedtime gap between them, to produce said time gap between each pair ofconsecutive gate signals.
 22. An integrated gate driver for performingemission operations of a display, the gate driver comprising: a sourceof first and second clock signals each, having alternating active andinactive portions configured such that when one is active the other isinactive and active signals do not overlap; a source for a start tokensignal and an inverse start token signal for input into a first circuitblock; integrated within a backplane of the display alternating odd andeven circuit blocks daisy chained together such that the output of onecircuit block is connected to the input of the next circuit block andeach circuit block receives as inputs both first and second clocksignals, wherein each circuit block includes a capacitor and a thin filmtransistor and is configured to produce an active output one clock cycleafter an active signal is received and an inactive output at all othertimes.
 23. The integrated gate driver of claim 22 configured for usewith a display comprising p-type transistors so that an active signalcorresponds with a high voltage and an inactive signal corresponds witha low voltage.
 24. The integrated gate driver of claim 22 wherein thealternating circuit blocks are configured to select a line of pixels fortwo clock cycles in order to allow time for the pixels to settle beforebeing programmed.
 25. A method of producing gate signals from a gatedriver integrated with the backplane of an active matrix organic lightemitting diode (AMOLED) display, said method comprising producing firstand second clock signals each having alternating active and inactiveportions configured such that when one of said clock signals is activethe other of said clock signals is inactive, and active portions of saidfirst and second clock signals do not overlap; producing gate signalsfrom a daisy chain of circuits integrated within said backplane, each ofsaid circuits including a capacitor and a thin film transistor, and eachof said circuits except the last circuit in the daisy chain having anoutput coupled to the input of an adjacent circuit in the daisy chain;supplying a start token signal to an input of a first circuit in saiddaisy chain; and producing a gate signal from each of said circuits,each gate signal being produced one clock cycle after said start tokensignal or an active portion of one of said clock signals is received.26. The method of claim 25 in which the AMOLED display comprises p-typetransistors so that an active signal corresponds to a low voltage and aninactive signal corresponds to a high voltage.
 27. The method of claim25 in which said gate signals are active low for selecting or addressingp-type thin film transistors.
 28. The method of claim 25 in which saidgate signals are active high for selecting or addressing n-type thinfilm transistors.
 29. The method of claim 25 which produces consecutivegate signals with a predetermined time gap between each pair ofconsecutive gate signals.
 30. The method of claim 29 in which saidactive portions of said first and second clock signals have apredetermined time gap between them, to produce said time gap betweeneach pair of consecutive gate signals.